1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device operating synchronously with an external clock input from an external source.
2. Description of the Background Art
In order to deal with demands of higher operating speed and larger data capacity for semiconductor devices, a technology has been employed, in which a plurality of semiconductor devices mounted on one system are collaboratively operated in synchronization with each other for efficient entire operation.
In such a system, each semiconductor device is required to perform an instructed internal operation synchronously with a clock signal common to the entire system (hereinafter also referred to as an external clock signal).
Therefore, a semiconductor device in which synchronous operation is required generally includes a control clock generating circuit for generating an internal control clock (hereinafter also simply referred to as a control clock) for controlling operations of internal circuits at a timing synchronous with the external clock.
FIG. 27 is a block diagram showing a configuration of a conventional control clock generating circuit 300. Control clock generating circuit 300 generates control clocks ISG1 and ISG2 synchronously with an external clock CLK.
Referring to FIG. 27, control clock generating circuit 300 includes a flip-flop 310 taking in a command signal CMD to generate a command clock CLKM in response to an activation timing of external clock CLK, and a pulse generating circuit 320 generating a reference clock pulse CLKP activated for a certain period in response to an activation of command clock CLKM.
Command signal CMD is activated when a command is provided to a semiconductor device including control clock generating circuit 300. Thus, command clock CLKM output from flip-flop 310 is updated in its signal level for each activation timing of external clock CLK, and is activated to a high level in a clock cycle in which a command is provided. As to signal levels of a clock and a control signal, high level and low level are hereinafter indicated as H level and L level respectively.
FIG. 28 is a circuit diagram showing a configuration of a pulse generating circuit 320.
Referring to FIG. 28, pulse generating circuit 320 includes a delay stage 322 for delaying command clock CLKM, and a logic gate 324 outputting a result of AND logical operation between an output of delay stage 322 and command clock CLKM as reference clock pulse CLKP.
Delay stage 322 includes an odd number of inverters. Delay stage 322 delays command clock CLKM by a delay time Th corresponding to the number of the inverters. This makes reference clock pulse CLKP a one shot pulse which is activated (to H level) for Th period in response to a transition of command clock CLKM from L level to H level. The activation period of a clock represented by the reference clock pulse is hereinafter also simply referred to as a pulse width.
Referring again to FIG. 27, reference clock pulse CLKP is fed to a delay circuit 330. Delay circuit 330 includes a plurality of delay units 340 connected in series. Each delay unit 340 is constituted by, for example, identical inverters in a predetermined even number. An output of each delay unit is provided with a tap. Hereinafter, a reference character TP is used for generic indication of each tap, and a particular tap is denoted with subscripts, such as TPa, TPb and so forth.
Such a configuration allows reference clock pulse CLKP delayed stepwise by delay time tdf to be taken out by selecting tap TP. An output from each tap is amplified by a signal buffer 345.
An internal control clock generating circuit 350 generates a control clock based on a signal taken in from each tap TP in delay circuit 330. As an example of the control clock, ISG1 and ISG2 are representatively shown in FIG. 27.
Internal control clock generating circuit 350 includes a logic gate 352 outputting an OR operation result of output signals of taps TPb and TPe. Logic gate 352 outputs control clock ISG1.
Internal control clock generating circuit 350 further includes a logic gate 354 outputting an OR operation result of output signals of taps TPa and TPd, a logic gate 356 outputting an OR logic operation result of output signals of taps TPc and TPf, and a logic gate 358 outputting an OR logical operation result of output signals of logic gates 354 and 356. Logic gate 358 outputs control clock ISG2.
Thus, a control clock activated in response to an activation of the reference clock pulse can be generated by OR operation between a plurality of tap outputs whose activation periods overlapped with each other. If a number of tap outputs are used in generating the control clock having a relatively long pulse width such as control clock ISG2 can be generated.
However, in a conventional control clock generating circuit 300, the pulse width of reference clock pulse CLKP corresponds to a certain time period determined by the number of inverters constituting delay stage 322. Further, a unit time tdf applied stepwise at delay circuit 330 also corresponds to a certain time period dependent on the number of inverters constituting delay unit 340.
Therefore, when a semiconductor device on which control clock generating circuit 300 is mounted is applied to various systems, it may be difficult to generate a control clock corresponding to a change of an operating frequency, i.e., a period of external clock CLK.
FIGS. 29 and 30 are timing charts illustrating a problem of a conventional control clock generating circuit 300 corresponding to variation of the operating frequency, i.e., the period of external clock CLK.
FIG. 29 shows an example where the operating frequency is relatively low, that is, the period of external clock CLK is relatively long.
Referring to FIG. 29, the period of external clock CLK is T0. In a clock cycle in which a command is provided, reference clock pulse CLKP is activated for a certain time period Th in response to the activation of external clock CLK at time t1. Reference clock pulse CLKP is delayed stepwise per unit delay time tdf in delay circuit 330, and is output from each tap TP.
Control signal ISG1 is generated by logic gate 352 in response to a signal output from TPb and TPe of a plurality of taps TP provided at delay circuit 330. An output of tap TPb rises to H level at time t2, and falls to L level at time t4. A difference of propagation delays between a leading edge and a trailing edge of a transistor in the delay unit may, as shown, make the interval between time t2 and time t4 longer than pulse width Th of reference clock pulse CLKP.
At t3 preceding time t4, an output of tap TPe rises to H level. An output signal of tap Tb starts to fall after a certain time period Th from time t3, and changes to L level at time t4. As a result, control clock ISG1 can be a control signal activated for a period from time t2 to time t5 in one clock cycle.
FIG. 30 shows an example where an operating frequency is relatively high, that is, a period of external clock CLK is relatively short.
Referring to FIG. 30, a period T0xe2x80x2 of external clock CLK is shorter than period T0 of external clock CLK shown in. FIG. 29. As in the case with FIG. 29, reference clock pulse CLKP is activated to H level for a certain period Th in response to an activation of external dock CLK at time t1 in a clock cycle to which a command is applied.
Reference clock pulse CLKP is fed to delay circuit 330 as in the case with FIG. 29, and can output reference clock pulse CLKP delayed stepwise per unit delay time tdf at each tap of delay circuit 330.
However, for pulse width Th of reference clock pulse CLKP and unit delay time tdf set at delay circuit 330, the operating frequency, i.e., the period of external clock CLK is independent of variations, having the same value as the one in FIG. 29. Thus, the fact that pulse width Th of reference clock pulse CLKP and unit delay time tdf at delay circuit 330 are constant independent of the period of external clock CLK results in a problem described below.
As in the case with FIG. 29, an output of tap TPb is changed to H level at time t2, and starts to fall after a predetermined time period Th. As a result, at time t4, the output of tap TPb is changed to L level. Also in the subsequent clock cycle, if a command is applied, tap TPb is again changed to H level after period T0xe2x80x2 of the external clock has passed since time t1.
The output of tap TPe is changed to H level at time t3, and starts to fall after Th has passed since time t3. It is then changed to L level at time t5.
Thus, because pulse width Th of reference clock pulse CLKP is constant while external clock period T0xe2x80x2 is shortened, a problem arises in which the output of tap TPb is changed to H level corresponding to a subsequent clock cycle before time t5 at which the output of tap TPe is completely changed to L level.
This makes control clock ISG1 continuous between two successive clock cycles. Thus, at the second clock cycle, an operation of internal circuits in response to the leading edge of control clock ISG1 cannot be performed as prescribed.
Further, because unit delay time tdf is a constant independent of the frequency of external clock CLK, the number of taps available for adjusting generation timing of a control clock in a clock cycle will be less when operated with high frequency, that is, when the period of external clock CLK is short. This lowers a degree of freedom for timing setting of activation and inactivation of a control clock for instructing operational timing for the internal circuits.
It is an object of the present invention to provide a semiconductor device operating synchronously with an external clock, including a control clock generating circuit generating a control clock determining an operational timing of an internal circuit at an appropriate timing corresponding to an external clock frequency.
According to one aspect of the present invention, a semiconductor device operating synchronously with an input clock repeating a transition between a first state and a second state in a certain period includes a control clock generating circuit and an internal circuit.
The control clock generating circuit generates a control clock synchronously with the input clock. The control clock generating circuit is activated in response to the transition of the first state of the input clock, and includes a first pulse generating circuit generating a reference clock pulse for which an activation state is maintained for a predetermined period set in accordance with the certain period, a first delay circuit delaying stepwise the reference clock pulse from the first pulse generating circuit to output a plurality of delayed clock pulses, and a second pulse generating circuit generating the control clock based on at least two of the plurality of delayed clock pulses. The internal circuit performs a predetermined operation in response to the control clock.
According to another aspect of the present invention, a semiconductor device operating synchronously with an input clock repeating first and second state transitions between a first state and a second state by a certain period includes an internal circuit and a control clock generating circuit. The internal circuit performs a predetermined operation in response to a first command and a second command provided from the first command after predetermined clock cycles of said input clock. The control clock generating circuit takes in the first and second commands to generate a control clock for rendering the internal circuit perform the predetermined operation in response to the first state transition of the input clock. The control clock generating circuit includes a period detecting circuit detecting the certain period during L clock cycles (L is a natural number), that is at least shorter than said predetermined cycles, after the first command is received, a first pulse generating circuit activated in response to the first state transition of the input clock to generate a reference clock pulse for which an activation state is maintained for a predetermined period set in accordance with the certain period detected by the period detecting circuit, a first delay circuit having a plurality of first delay units connected in series and each having unit delay time set in accordance with the certain time period and delaying stepwise the reference clock pulse from the first pulse generating circuit to output a plurality of delayed clock pulses, and a second pulse generating circuit generating the control clock based on at least two of the plurality of delayed clock pulses.
Therefore, a main advantage of the present invention is to generate a control clock controlling operational timing of an internal circuit based on delayed clock pulses obtained by stepwisely delaying a reference clock pulse activated in response to an input clock and having an activation period in accordance with a period of the input clock. Therefore, it is advantageous that the control clock can be generated inside of the semiconductor device at an appropriate timing corresponding to the frequency of the input clock.
Further, the period of the input clock is detected during a period from generation of the first command to generation of the second command, so that the control clock can be generated at an appropriate timing corresponding to the frequency of the input clock before the operational command is executed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.